The present application relates to an interconnect structure for use in semiconductor technology and a method of forming the same. More particularly, the present application relates to an interconnect structure having reduced back-end-of-the-line (BEOL) resistance and capacitance and a method of forming the same.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure, which may also be referred to as an interconnect structure, typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
Interconnect structures in integrated circuits induce a delay in the propagation of the information between semiconductor devices such as transistors. To reduce this delay, the interconnect structures should possess the lowest capacitance possible.